Digital phase-locked loops (PLLs) provide a number of advantages over conventional analog PLLs. Digital PLLs can be easier to port from one semiconductor process to another semiconductor process because all that is required are fairly simple code/parameter changes. In contrast, analog PLLs usually have to be completely redesigned when moving to another semiconductor process. Also, as feature sizes continue to decrease, analog PLLs suffer from low output resistances, large leakage currents caused by large capacitors, and poor control over device parameters.
The digitally controlled oscillators (DCOs) inside digital PLLs can introduce quantization noise which can cause dithering at the output of the digital PLL. Moreover, there is a tradeoff in this quantization noise. If the DCO step size is made smaller, there is less dithering jitter. However, the system is slower to react to large power supply changes which cause power-supply-induced jitter (PSIJ).